Adv Mater 2012,

24:5104–5110.CrossRef Competing interests The authors declare that they have no competing interests. Authors’ contributions JL designed and performed all the experiments and wrote the manuscript. ZZ helped prepare the gold nanoclusters/nanoparticles. ZL, CZ, and XW contributed to cell imaging. KW finished the MTT assay. GG and PH participated in the design of the study and discussion. DC conceived the study and participated in its design and coordination. All authors read and approved the final manuscript.”
“Background Recently, cerium oxide (CeO2) is proposed as a possible gate dielectric material in selleckchem metal-oxide-semiconductor and memory devices for next generation devices [1, 2]. This is because CeO2 can be epitaxially grown on a Si (111) surface [3] and also because its high ability for oxygen storage makes CeO2 one of the most important automobile exhaust catalysts [4]. CeO2 has a high dielectric constant [5, 6] and may be used as a high-k gate

dielectric to suppress gate leakage current. CeO2 has also been added to HfO2 in order to stabilize the high-k cubic and tetragonal phases for potential applications in sub-32-nm-node complementary metal oxide semiconductor (CMOS) devices [7, 8]. In terms of microelectronic applications, atomic layer deposition (ALD) is the most attractive technique for the deposition of CeO2. This is due to its ability to deposit large areas of high-uniformity thin films, good doping control, and

Osimertinib superior conformal PI3K Inhibitor high throughput screening step coverage on highly non-planar substrates [9]. In ALD, metal alkoxides have the major advantage of high reactivity with H2O, thus avoiding the formation of a low-permittivity interfacial layer during the ALD of high-k dielectrics [7]. Figure 1 Grain sizes for as-deposited CeO 2 samples under different deposition temperatures (150° C, 200° C, 250° C, 300° C, and 350° C). XRD patterns are shown in the inset. Grain sizes (extracted from XRD data) increased following the increasing deposition temperatures. Figure 2 XRD patterns for the 250° C samples (green for the as-deposited and blue for the post-deposition annealing). The grain size of the annealed sample (9.55 nm) increased compared to the as-deposited sample (8.83 nm), which suggests that post-deposition annealing in vacuum causes an increase in the size of the crystalline grains. Figure 3 Raman spectrum of CeO 2 samples deposited under different temperatures (150° C, 200° C, 250° C, 300° C, and 350° C). Raman spectrum results are consistent with XRD data (inset of Figure 1): larger grain sizes were observed as the deposition temperature increases. Figure 4 Capacitance-voltage (C-V) measurements of the as-deposited (AD) and the annealed (ann) samples under different frequencies. Frequencies: 100 Hz, 1 kHz, 10 kHz, 100 kHz, and 1 MHz.